Microchip has unveiled the architecture for a new class of SoC FPGAs that combine the industry's lowest power, mid-range PolarFire® FPGA family with a hardened microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA). Announced at the 2018 RISC-V Summit in Santa Clara, the PolarFire SoC architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. The presentation will discuss this fully customizable, programmable RISC-V platform that allows embedded developers to create innovative Linux-based SoCs tailored for their domain-specific requirements.
