Getting Started with RISC-V Paris has ended

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Getting Started with RISC-V Paris

09:30 CEST

Registration & Breakfast Open Platform

10:00 CEST

Introduction to RISC-V - Calista Redmond, RISC-V Foundation Master Stage

10:20 CEST

Rocinante: Motor Control SoC with integrated RISC-V Core - Göran Eggers, Trinamic Motion Control Master Stage

10:40 CEST

Embedded Software Development for RISC-V Based SoC - Rocco Jonack, Minres Technology GmbH Master Stage

11:00 CEST

SCRx family of the RISC-V compatible processor IP by Syntacore - Alexander Redkin & Pavel Khabarov, Syntacore Master Stage

11:20 CEST

Morning Break TBA

11:50 CEST

RISC-V SoC FPGA Brings Real-Time to Linux - Jeff Laporte, Microchip Technology Master Stage

12:10 CEST

Machine Learning on Battery Operated Devices at the Very Edge Using a Multi-core RISC-V Based Processor - Martin Croome, GreenWaves Master Stage

12:30 CEST

Fast Start into RISC-V for AIoT with A+ Core - Florian Wohlrab, Andes Technology Master Stage

12:50 CEST

Lunch TBA

13:50 CEST

RISC-V SoftCPU Contest Winners Announced: Sponsored by Thales Group & Microchip - Presented by Bertrand Tavernier, VP Thales Software Research & Technologies Master Stage

14:00 CEST

SweRV Core & CHIPS Alliance Initiatives - Ted Marena, Western Digital Master Stage

14:20 CEST

Breaking the Barriers of Safety Critical Systems Thanks to RISC-V - Pierre-Jean Turpeau & Daniel Gracia Pérez, Thales Group Master Stage

14:40 CEST

High Reliability C/Ada/SPARK Solutions for Software Development on RISC-V - Fabien Chouteau & Le Yin Kéu, AdaCore Master Stage

15:00 CEST

An Overview of Embedded Microprocessor Security - Dany Nativel, SiFive Master Stage

Timezone Getting Started with RISC-V Paris
Europe/Paris
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